Synchronous dynamic random access memory devices, referred to as SDRAMs, are now widely being used in personal computers and other data processing systems. As is well known to those having skill in the art, an SDRAM uses a clock to synchronize signal input and output on a memory device. The clock is coordinated with the clock of a central processing unit or microprocessor, so that the timing of the memory device and the timing of the central processing unit are synchronous. An SDRAM can increase the overall system performance of a computer by reducing the time to execute commands and transmit data. SDRAMs may include an on-chip burst counter that can be used to increment column addresses for very fast burst access. To work with high clock speeds, SDRAMs may include two or more internal banks. This allows one bank to get ready for access while the other bank is being accessed. Thus, new memory accesses can be initiated before the preceding access has been completed.
SDRAMs use clock buffers, which is a form of an input buffer, to receive an external clock signal and generate an internal clock signal which in turn is used to control an output buffer. Accordingly, for an SDRAM, the time tSAC between receiving the external clock signal in the clock buffer and outputting data through the output buffer, and the time tOH for which previous data is maintained to fetch the output data, may be important parameters. However, when a tSAC path is designed to decrease tSAC of the SDRAM, the tOH margin may be reduced. Accordingly, in order to decrease the tSAC and ensure an adequate tOH margin, a change of data output speed according to a change of the power supply voltage VCC may be obtained by using an internal power supply voltage IVC in the clock buffer.
FIG. 1 is a circuit diagram of a conventional input buffer used as a clock buffer in an SDRAM. Referring to FIG. 1, a conventional input buffer includes a differential amplifier 11 that amplifies the difference between a reference voltage VREF and an external input signal INPUT. A switching portion 13 supplies an internal power supply voltage IVC to the differential amplifier 11 when a control signal PBUFC is active.
The differential amplifier portion 11 may be a conventional differential amplifier. The switching portion comprises a PMOS transistor P11 including a source to which the internal power supply voltage IVC is applied, a gate to which the control signal PBUFC is applied, and a drain connected to the differential amplifier 11. The internal power supply voltage IVC is generated by an internal power supply voltage generator of an SDRAM, using an external power supply voltage EVC, and has a predetermined level regardless of the external power supply voltage EVC.
It is also well known that SDRAMs can operate using Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL). As is well known to those having skill in the art, both LVTTL and SSTL are bus termination techniques. SSTL was created by the JEDEC Committee as an upgrade for LVTTL. An SSTL-based SDRAM design can reduce the heat generated, as well as improve the performance thereof. See U.S. Pat. Nos. 5,696,456 to Lee entitled "Enhanced Low Voltage TTL Interface " and U.S. Pat. No. 5,530,379 to Konishi et al. entitled "Output Buffer Circuit That Can be Shared by a Plurality of Interfaces and a Semiconductor Device Using the Same".
Under LVTTL interface conditions of an SDRAM, the input signal INPUT and the reference voltage VREF received by the input buffer are maintained at a constant level even though the external power supply voltage EVC changes, to thereby allow the input buffer to operate normally. That is, since the internal power supply voltage IVC is maintained at a constant level and the reference voltage VREF and the input signal INPUT received by the gate of each of the NMOS transistors N11 and N12 of the differential amplifying portion 11 are maintained at a constant level, the PMOS transistors P12 and P13 and the NMOS transistors N11 and N12 of the differential amplifying portion 11 can operate normally.
However, under SSTL interface conditions, the input signal INPUT and the reference voltage VREF received by the input buffer may change according to the external power supply voltage EVC. Accordingly, the input buffer may not operate properly. That is, the internal power supply voltage IVC is maintained at a constant level and the input signal INPUT and the reference voltage VREF change according to the external power supply voltage EVC. Accordingly, the PMOS transistors P12 and P13 and the NMOS transistors N11 and N12, of the differential amplifing portion 11 may operate improperly. For example, when the input signal INPUT and the reference voltage VREF increase, the voltage between the gate and source of each of the PMOS transistors P12 and P13 may become lower than that of the NMOS transistors N11 and N12. Therefore, the output signal BIN of the differential amplifying portion 11 may remain at logic "low", so that the input buffer may operate improperly.